The present invention relates to a circuit design field, and more particularly, to a method and an apparatus for fixing a hold time violation in a circuit.
When a circuit (e.g., an integrated circuit, etc.) is designed, after completion of placement and wiring of various elements (e.g., various gate circuits and various standard units) of the circuit, a timing analysis is performed on the circuit to check whether there is a timing violation in the circuit. The timing violation includes a setup time violation, a hold time violation, etc. Setup time indicates time during which data at an input port of a gate circuit should remain stable before a clock edge arrives at the gate circuit. If the time during which the data at the input port of the gate circuit remains stable is less than the required setup time, then the setup time violation occurs, which will render that the data can not be input into the gate circuit correctly when the clock edge arrives at the gate circuit. As known in the art, it may be judged whether the setup time violation occurs through a setup slack. Specifically, when the setup slack is less than 0, it can be determined that the setup time violation occurs. Hold time indicates time during which the data at the input port of the gate circuit should remain stable after the clock edge arrives at the gate circuit. If the time during which the data at the input port of the gate circuit remains stable after the clock edge arrives at the gate circuit is less than the required hold time, then the hold time violation occurs, which will also render that the data cannot be input into the gate circuit correctly. As known in the art, it can be judged whether the hold time violation occurs through a hold slack. Specifically, when the hold slack is less than 0, it can be determined that the hold time violation occurs. When any of the above timing violations occurs, it is necessary to fix the timing violation in order to enable the circuit to work normally.
Usually, the hold time violation is fixed at a final stage of circuit design, namely, after all elements and input/output pins thereof have been placed and fixed and the setup time violation and other timing violations have been fixed. In a conventional method for fixing the hold time violation, an element where the hold time violation occurs in the circuit is found and a delay element is inserted at the element, so as to fix the hold time violation. However, there are several problems in the conventional method for fixing the hold time violation. Firstly, as a scale and complexity of the circuit increase, the circuit comprises a large number of elements, causing high element densities in some regions in the circuit; moreover, in such regions, influence of element characteristic variations caused by manufacturing processes is relatively large, so a lot of hold time violations may occur. If delay elements are inserted in these regions in order to fix the hold time violations, the element densities in these regions will be further increased, and congestion will be caused in wiring of circuit elements. In addition, it is often necessary to move elements which have been placed and/or input/output pins thereof in the conventional method for fixing the hold time violation, which is apt to cause a new timing violation.